This invention relates to tri-state output buffer circuits, and in particular, to a tri-state output buffer circuit utilizing dynamic depletion mode MOS devices.
Current, tri-state output buffers typically use either enhancement mode MOS devices or a combination of enhancement and depletion mode devices. These configurations are deficient in that they have output levels which are either less than the positive voltage supply or else suffer from slow rise time characteristics. The enhancement mode configuration suffers from the former drawback and the enhancement/depletion mode configuration suffers from the latter.
The technique of using dynamic or pulsed use of depletion-mode MOSFET devices has been described in several publications. See for example, "Dynamic Depletion Mode: An E/D MOSFET Circuit Method for Improved Performance", by R. W. Knipper, IEEE Journal of Solid-State Circuits, Vol. SC-13, No. 5, October 1978, pp 542-547 and also "Dynamic Depletion Mode: An E/D MOSFET Circuit Method" 1978 IEEE International Solid-State Circuits Conference, pp. 16.noteq.17, by the same author. These publications describe a number of circuits including drivers employing the dynamic depletion mode (DDM) technique, but not in a tri-state buffer configuration.